Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
Power electronics is an application of solid-state electronics for control and conversion of electric power. Power electronic products capture a big majority of electronics market share today, which is attributed to diverse range of applications they cater to, which in turn is enabled by advance power semiconductor device technologies. As well known in the art, semiconductor devices are electronic components that exploit electronic properties of semiconductor materials, principally silicon, germanium, and gallium arsenide, as well as organic semiconductors. Semiconductor devices have replaced thermionic devices (vacuum tubes) in most applications. They use electronic conduction in solid state as opposed to gaseous state or thermionic emission in a high vacuum. Semiconductor devices are manufactured both as single discrete devices and as integrated circuits (ICs), which consist of a few (as low as two) to billions of devices manufactured and interconnected on a single semiconductor substrate, or wafer.
Key semiconductor device technologies can be classified by their base materials such as Silicon (Si), Gallium arsenide (GaAs), Gallium Nitride (GaN), Silicon Carbide (SiC) and diamond. While Si, SiC and GaAs technologies are well established, GaN based devices and systems for high power and/or high frequency (RF) applications are currently entering the market. FIG. 1 illustrates an exemplary view of power electronics spectrum, its applications and exemplary trend of semiconductor device technologies used in these power electronics.
Growth and development of technology has consistently provided new and advanced types of semiconductor device technologies with wide range of technological applicability for the power electronics. One such semiconductor device technologies is a High-electron-mobility transistor (HEMT), also known as heterostructure FET (HFET) or modulation-doped FET (MODFET). The HEMT is a field-effect transistor incorporating a junction between two materials with different band gaps (i.e. a heterojunction) as the channel instead of a doped region (as is generally the case for MOSFET). A commonly used material combination is GaAs with Aluminium (Al) GaAs, though there is wide variation, dependent on the application of the device. Devices incorporating more indium generally show better high-frequency performance, while in recent years, gallium nitride HEMTs have attracted attention due to their high-power performance. Devices incorporating more indium generally show better high-frequency performance, while in recent years, gallium nitride (GaN) HEMTs have attracted attention due to their high-power performance.
It is expected that HEMT using GaN as its wide band gap semiconductor will be applied in diverse, power electronics/green ICT systems because of its high efficiency. GaN HEMT utilizes high-density two-dimensional electron gas (2DEG) accumulated in boundary layer between GaN and AlGaN through their piezoelectric effect and natural polarization effect, which makes it possible to realize a low on-state resistance (Ron). Combined with a high breakdown voltage, GaN HEMT indicates a superb performance as a power device. After the development of GaN HEMT technology for power amplifiers of mobile base stations, it was expanded to radar sensor applications. Further, expansion of its application is expected in the field of power conversion, i.e. in equipment such as server power systems. While the development of GaN HEMT technology has been promoted with focus on conventional “high output power”, further advantages such as high efficiency and low energy consumption have been attracting much attention in recent years.
FIGS. 2-4 illustrate exemplary GaN HEMT devices that are available in prior-art, and which are currently being adopted by different manufacturers such as but not limited to, GaN System Inc, Engineered Plastic Components, Inc. (EPC), Transphorm, and the like. FIGS. 2A and 2B illustrate e-mode or normally-OFF GaN HEMT device with P—GaN (reverse polarization) layer in the gate stack (under gate electrode). Such layer keeps the channel depleted when gate to source voltage is below threshold voltage. However, when a sufficiently high gate voltage (higher than threshold voltage) is applied, device turns-on and offers switching operation. Though the design offers easy e-mode solution, it requires a P—GaN growth over standard AlGaN/GaN HEMT stack. Moreover, since the gate is 50-100 nm away from the 2DEG, the gate to channel control suffers in this architecture. Hence, this architecture is expected to suffer from slower turn-on and larger gate voltage swing for switching operation, which can also add to dynamic or turn-on losses. When gate-to-source voltage is below threshold, due to reverse polarization, channel is depleted from electrons. When the same exceeds threshold voltage, the channel inverts/accumulates electrons, which form a channel between accesses and drift regions. Such devices as illustrated in FIGS. 2A and 2B are mostly adopted by GaN Systems and EPC as known in the prior-art.
FIG. 3 illustrates another device available in the prior-art with a Si LDMOS in series (Cascode configuration) with normally-ON HEMT device. Source and Gate of Si LDMOS works as the source and gate of the combined switch, whereas drain of HEMT works as the drain terminal of this switch. Gate and source of HEMT and drain of Si-LDMOS are tied together, however are not available for contacting to outside world. Here HEMT device is to block higher voltages (increase breakdown voltage), whereas Si-LDMOS device is for normally-OFF operation. This design too offers an e-mode (normally-OFF) operation, however requires devices from two technologies, i.e. Si-LDMOS and GaN HEMT. Due to cascode operation, device performance is expected to be lower and limited to channel characteristics of Si-LDMOS device when compared to e-mode GaN HEMT. Last but not the least, this configuration is known to be less reliable both under extended stress as well as under short circuit stress conditions. Such devices are to increase breakdown voltage, whereas Si LDMOS device is for normally-OFF operation. Such devices as illustrated in FIG. 3 are mostly adopted by Transphorm.
FIG. 4 illustrates another device as disclosed in U.S. Pat. No. 7,449,762 B1, which has a recess and a P—GaN buffer layer. This forms RESURF junction with N—AlGaN layer. Here recess gate is in direct contact with P—GaN layer. However, such device includes certain technical drawbacks and hence may not technically fit to provide desired functionalities. One of the major technical problems available in the device of U.S. Pat. No. 7,449,762 B1 is attributed to gate stack being directly in contact with P—GaN layer, making channel formation in this device very slow. Moreover, due to unavailability of minority carriers (electrons) in P—GaN buffer, formed channel electron density will be very small (can be almost negligible depending of P—GaN doping), which will give rise to ON resistance. Further, as the AlGaN layer is directly above P—GaN buffer, the carrier density in 2DEG is expected to be very less, which will further give rise to ON resistance. Also, high breakdown voltage would require higher P—GaN doping, however this can deplete 2DEG. Furthermore, attributed to very thin N-doped layer above P—GaN buffer (typical AlGaN is 25-40 nm thick), the device of U.S. Pat. No. 7,449,762 B1 will offer significantly lower breakdown voltage when compared to device without P-doped buffer (i.e. with N-doped buffer). In view of such technical problems in the device of U.S. Pat. No. 7,449,762 B1 a person skilled in the art would clearly understand that it would not be an exaggeration to conclude that this prior art device would offer significantly inferior breakdown voltage vs. ON-resistance trade-off, when compared to other prior art devices
There is therefore a need to provide a new, improved, efficient, and technically advanced HEMT device that can provide higher breakdown voltage when compared to the designs available in the prior-art without affecting performance figure of merits. Further, new HEMT device should offer improved breakdown voltage as compared to ON-resistance trade-off, improved short channel effects, improved gate control over channel, improved switching speed for a given breakdown voltage, and improved device reliability. Furthermore, the new HEMT device should lower gate-to-drain (miller) capacitance and should be available at low cost.
In some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.
As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description of all groups used in the appended claims.